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TECHNICAL DATA
IN74HC157A
Quad 2-Input Data Selectors/Multiplexer
The IN74HC157A is identical in pin out to the LS/ALS157. The device inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LS/ALSTTL outputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in non inverted form. A high level on the Output Enable input sets all four Y outputs to a low level. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION IN74HC157AN Plastic IN74HC157AD SOIC IZ74HC157A Chip TA = -55 to 125 C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output Enable PIN 16 =VCC PIN 8 = GND H L L Select X L H Outputs Y0-Y3 L A0-A3 B0-B3
X=don't care A0-A3, B0-B3=the levels of the respective Data-Word Inputs
INTEGRAL
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IN74HC157A
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
**
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
INTEGRAL
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IN74HC157A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4.0 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 A A V V Unit
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
VIL
V
VOH
V
VOL
Maximum Low-Level Output Voltage
VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
VIN=VCC or GND VIN=VCC or GND IOUT=0A
INTEGRAL
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IN74HC157A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)
VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1and 4) Maximum Propagation Delay , Select to Output Y (Figures 2 and 4) Maximum Propagation Delay , Output Enable to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 105 21 18 110 22 19 100 20 17 75 15 13 10 85C 130 26 22 140 28 24 125 25 21 95 19 16 10 125C 160 32 27 165 33 28 150 30 26 110 22 19 10 Unit ns
tPLH, t PHL
ns
tPLH, t PHL
ns
tTLH, t THL
ns
CIN
pF
Typical @25C,VCC=5.0 V 33 pF
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INTEGRAL
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IN74HC157A
EXPANDED LOGIC DIAGRAM
INTEGRAL
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IN74HC157A
CHIP PAD DIAGRAM IZ74HC157A
Pad size 0.120 x 0.120 mm (Pad size is given as per passivation layer) Thickness of chip 0,460,02 mm
PAD LOCATION
Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Symbol SELECT A0 B0 Y0 A1 B1 Y1 GND Y2 B2 A2 Y3 B3 A3 OUTPUT ENABLE Vcc X 0.143 0.143 0.143 0.377 0.644 0.848 1.132 1.132 1.131 1.101 1.122 0.650 0.442 0.153 0.143 0.143 Y 0.668 0.443 0.173 0.133 0.133 0.133 0.244 0.468 0.748 1.036 1.27 0.311 1.311 1.271 1.069 0.838 Pad size 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.159 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.106 0.106x0.159
INTEGRAL
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